// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +xtheadbb -emit-llvm %s -o - \
// RUN:     | FileCheck %s  -check-prefix=RV32XTHEADBB

// RV32XTHEADBB-LABEL: @clz_32(
// RV32XTHEADBB-NEXT:  entry:
// RV32XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
// RV32XTHEADBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// RV32XTHEADBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// RV32XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
// RV32XTHEADBB-NEXT:    ret i32 [[TMP1]]
//
int clz_32(int a) {
  return __builtin_riscv_clz_32(a);
}

// RV32XTHEADBB-LABEL: @clo_32(
// RV32XTHEADBB-NEXT:  entry:
// RV32XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
// RV32XTHEADBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// RV32XTHEADBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// RV32XTHEADBB-NEXT:    [[NOT:%.*]] = xor i32 [[TMP0]], -1
// RV32XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
// RV32XTHEADBB-NEXT:    ret i32 [[TMP1]]
//
int clo_32(int a) {
  return __builtin_riscv_clz_32(~a);
}
